High bandwidth controller memory buffer (CMB) for peer to peer data transfer
US11733917B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Sep 17, 2020 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Oct 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A PCIe architecture is disclosed incorporating a controller memory buffer (CMB). Write data is written to the CMB and is not read out for processing upon receiving a write command for the write data. The data is read out of the CMB and processed to obtain processed data upon receiving feedback from a NAND channel controller. The processed data may be written directly to the NAND channel controller or may be written to a light write buffer that is read by the NAND channel controller. The processed data may be written to a light write buffer functioning as a cut through buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.