Memory interface having multiple snoop processors
US11734177B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Aug 26, 2021 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Aug 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface for interfacing between a memory bus and a cache memory, comprising: a plurality of bus interfaces configured to transfer data between the memory bus and the cache memory; and a plurality of snoop processors configured to receive snoop requests from the memory bus; wherein each snoop processor is associated with a respective bus interface and each snoop processor is configured, on receiving a snoop request, to determine whether the snoop request relates to the bus interface associated with that snoop processor and to process the snoop request in dependence on that determination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.