Avoiding data routing conflicts in a machine learning accelerator
US11734549B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2020 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Jan 6, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compiler receives a description of a machine learning network (MLN) and generates a computer program that implements the MLN on a machine learning accelerator (MLA). To implement the MLN, the compiler generates compute instructions that implement computations of the MLN on different processing units (Tiles), and data transfer instructions that transfer data used in the computations. The compiler may statically schedule at least a portion of the instructions for execution by the Tiles according to fixed timing. The compiler may initially implement data transfers between non-adjacent Tiles (or external memories) by implementing a sequence of transfers through one or more intermediate Tiles (or external memories) in accordance with a set of default routing rules that dictates the data path. The computer program may then be simulated to identify routing conflicts. When routing conflicts are detected, the compiler updates the computer program in a manner that avoids the conflicts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.