Semiconductor device including plurality of patterns
US11735522B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2021 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Aug 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first metal wiring pattern area, and a second metal wiring pattern area that does not overlap the first metal wiring pattern area in a plan view. The first metal wiring pattern area includes a first pattern, the second metal wiring pattern area includes a second pattern that is spaced apart from the first pattern and includes one or more lines. The first metal wiring pattern area includes an assist pattern comprising one or more lines. The assist pattern is spaced apart from the second pattern, parallel with the second pattern, and is between the first pattern and the second pattern. One end of the assist pattern is connected to the first pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.