Semiconductor package and method of manufacturing the semiconductor package
US11735553B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2021 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Sep 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a support member, a semiconductor chip arranged in the support member such that a front surface and a backside surface of the semiconductor chip are exposed from a second surface of the support member and a first surface opposite to the second surface respectively, a lower redistribution wiring layer covering the second surface of the support member and including first redistribution wirings electrically connected to chip pads provided at the front surface of the semiconductor chip and vertical connection structures of the support member respectively, and an upper redistribution wiring layer covering the first surface of the support substrate, and including second redistribution wirings electrically connected to the vertical connection structures and a thermal pattern provided on the exposed backside surface of the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.