Low powered clock driving
US11736095B2 · kind B2 · utility
0Cited by
23References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2022 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Nov 15, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.