Field-programmable gate array (FPGA) for using configuration shift chain to implement multi-bitstream function
US11736107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2021 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Apr 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A field-programmable gate array (FPGA) for using a configuration shift chain to implement a multi-bitstream function includes a bitstream control circuit, a multi-bitstream configuration shift chain and a configurable module. The FPGA enables multi-bitstream storage configuration bits to latch configuration bitstreams by adjusting a circuit structure of a multi-bitstream configuration shift chain in a combination of a control logic of a bitstream control circuit for the multi-bitstream configuration shift chain, and outputs one latched configuration bitstream from a configuration output terminal to a configurable module through each multi-bitstream storage configuration bit as required, so that the configurable module implements a logic function corresponding to the configuration bitstream outputted by the multi-bitstream configuration shift chain. By switching output of different configuration bitstreams, the FPGA can perform a plurality of times of high-speed switching to implement different logic functions without downloading bitstreams from an off-chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.