Low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware

US11736594B2 · kind B2 · utility

Assignee

• Tata Consultancy Services Limited · IN

Inventors

• Dhaval Shah · Evansville, US
• Sunil PURANIK · Pune, IN
• Manoj Karunakaran Nambiar · Mumbai, IN
• Mahesh Damodar Barve · Pune, IN
• Ishtiyaque Shaikh · Thane, IN
• Piyush Manavar · Thane, IN
• Sharyu Vijay Mukhekar · Pune, IN

Key dates

• Filing date: Jun 16, 2021
• Grant date: Aug 22, 2023
• Expiry date: Nov 4, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L1/1628
• WIPO field: Digital communication
• WIPO sector: Electrical engineering

Abstract

A method and system of a low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware is disclosed. The need for low-latency communication in digital systems has increased drastically. The disclosed FPGA framework enables low-latency communication as a hybrid framework that supports both UDP & TCP communication. As known in art, TCP provides error checking support hence making TCP more reliable as compared to UDP, while UDP is faster but not reliable. Hence the disclosed low-latency FPGA framework latency utilizes the advantage of both UDP and TCP by utilizing UDP for its speed, while switching to TCP in case of a missing sequence in UDP. Further, the disclosed system proposes a TCP re-assembly middleware architecture for processing TCP with a lower-latency, wherein the TCP re-assembly middleware is an independent middleware that is a modular and a plug-play independent middleware.