Channel combining and time-division processing circuit of dual-plane pulse doppler radar seeker
US11740324B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Jan 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01S13/53
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The disclosure discloses a channel combining and time-division processing circuit of a dual-plane pulse Doppler radar seeker. The circuit includes a time-division control circuit configured to receive a time-division control signal, control input of an elevation difference channel signal and an azimuth difference channel signal, combine the elevation difference channel signal and the azimuth difference channel signal and output a combined difference channel signal, and a hybrid bridge circuit configured to receive a sum channel signal, combine channels for the sum channel signal and the combined difference channel signal and output signals on a combined channel. With the circuit of the disclosure, signals received from a sum channel, an azimuth difference channel and an elevation difference channel can be combined into received signals from two channels for processing with one received signal processing channel hardware omitted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.