Clock multiplexer device and clock switching method
US11740651B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Apr 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock multiplexer device includes first and second control circuitries and an output circuitry. The first control circuitry generates a first enable signal and a first signal according to a first clock signal and a first selection signal, and determines whether to output the first signal to be a first output clock signal according to a second selection signal and a second enable signal. The first and the second selection signals have opposite logic values. The second control circuitry generates the second enable signal and a second signal according to a second clock signal and the second selection signal, and determines whether to output the second signal to be a second output clock signal according to the first selection signal and the first enable signal. The output circuitry outputs one of the first output clock signal and the second output clock signal to be a final clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.