Convolutional network hardware accelerator device, system and method
US11740870B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 27, 2020 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Dec 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Multiple Accumulate (MAC) hardware accelerator includes a plurality of multipliers. The plurality of multipliers multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input. A result is generated based on the multiplication of the digit-serial input by the parallel input. An accelerator framework may include multiple MAC hardware accelerators, and may be used to implement a convolutional neural network. The MAC hardware accelerators may multiple an input weight by an input feature by sequentially multiplying individual digits of the input weight by the input feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.