Implementing crash consistency in persistent memory
US11740928B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 26, 2019 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Aug 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method according to one aspect includes receiving a request to perform a transaction in persistent memory; determining a correlation between volatile memory address locations in a volatile transaction cache and persistent memory locations in the persistent memory; performing the transaction within the volatile memory address locations of the volatile transaction cache; identifying modified volatile memory address locations in the volatile transaction cache that have been written during the transaction; logging, within the persistent memory, data within the modified volatile memory address locations; copying the data within the modified volatile memory address locations to corresponding persistent memory locations in the persistent memory, utilizing the determined correlation; and removing the logged data from the persistent memory, in response to determining that the copying has completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.