Semiconductor wafer fault analysis system and operation method thereof
US11741596B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2019 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Jun 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor wafer fault analysis system includes: a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type; a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map; a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; and a fault type analyzer. The database is updated based on the first and second pre-processed reference maps, and the fault type analyzer is to classify a fault type of a target map based on the updated database. The target map is generated by measuring a target wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.