Array substrate and display panel
US11741914B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 28, 2022 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Jul 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0223
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An array substrate and a display panel are disclosed in an embodiment of the present application. The array substrate includes a plurality of GOA units in cascade and a plurality of clock signal lines. The plurality of clock signal lines are arranged on one side of the GOA units and are arranged at intervals along a direction away from the GOA units. The plurality of GOA units are electrically connected to the plurality of clock signal lines, respectively. Wherein, a number of the GOA units electrically connected to each of the clock signal lines is equal. The array substrate reduces a resistance difference and a capacitance difference between the plurality of clock signal lines and alleviates a problem of dense horizontal lines by adjusting a number of stages of the GOA units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.