Barrier stacks for printed and/or thin film electronics, methods of manufacturing the same, and method of controlling a threshold voltage of a thin film transistor
US11742363B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2019 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Nov 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure pertains to a barrier stack for thin film and/or printed electronics on substrates having a diffusible element and/or species, methods of manufacturing the same, and methods of inhibiting or preventing diffusion of a diffusible element or species in a substrate using the same. The barrier stack includes a first barrier layer on the substrate, an insulator layer on the first barrier layer, a second barrier layer on the insulator layer in a first region of the substrate, and a third barrier layer on the insulator layer in a second region of the substrate and on the second barrier layer in the first region. Each of the second and third barrier layers has a thickness less than that of the first barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.