Semiconductor devices having an insulation layer in a recess and an impurity barrier layer extending along the insulation layer
US11742401B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Jun 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
Abstract
A semiconductor device may include a substrate including a recess, a gate insulation layer on a surface of the recess, an impurity barrier layer on a surface of the gate insulation layer to cover the surface of the gate insulation layer, a first gate pattern on impurity barrier layer to fill a lower portion of the recess, a second gate pattern on the first gate pattern in the recess, a capping insulation pattern on the second gate pattern to fill the recess, and impurity regions at the substrate adjacent to an upper sidewall of the recess. The impurity barrier layer may have a concentration of nitrogen higher than a concentration of nitrogen included in the gate insulation layer. The second gate pattern may include a material different from a material of the first gate pattern. A lower surface of the impurity regions may be higher than an upper surface of the first gate pattern. Thus, the semiconductor device may have good characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.