Backplane, preparation method with dual damascene steps
US11742467B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Jul 2, 2020 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Oct 31, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/0364
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A preparation method of a backplane includes: forming an insulating structure layer having a groove on a base substrate by a mask exposure process, the groove being used for accommodating a metal trace; and repeating a metal sub-layer forming step including an ashing process and a wet etching process multiple times to form the metal trace positioned in the groove.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.