Flip flop and design method for integrated circuit including the same
US11742838B2 · kind B2 · utility
2Cited by
11References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2022 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Mar 29, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop includes a first master latch in a first row, a second master latch in a second row, a first slave latch in the first row, and a second slave latch in the second row. The first master latch and the second master latch are adjacently disposed in the second direction, and the first slave latch and the second slave latch are adjacently disposed in the second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.