Noise disturbance rejection for power supply
US11742840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2022 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | May 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B15/00
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Apparatus and associated methods relate to a power supply noise disturbance rejection circuit (NDRC) having a first circuit reference potential (CRP1), a second circuit reference potential (CRP2), and a galvanic link conductively connecting CRP1 and CRP2 and providing a non-zero resistance return path for at least one current mode signal (CMS). In an illustrative example, a power supply monitor circuit (PSMC) may be referenced to CRP1 and a control circuit to CRP2. The PMSC may, for example, generate a voltage mode signal (VMS) relative to CRP1 and representing an output parameter of a power supply circuit (PSC), and convert the VMS into a first CMS (CMS1). The control circuit may, for example, generate a control signal for the PSC from CMS1. Various embodiments may advantageously attenuate a noise margin of a CMS presented at the control circuit by a factor of at least 10 relative to an equivalent VMS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.