Patent · US Active

Multi-phase clock generator and method thereof

US11742842B2 · kind B2 · utility

0Cited by
3References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 1, 2022
Grant dateAug 29, 2023
Priority date
Expiry dateSep 1, 2042

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03K5/15013
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A multi-phase clock generator is provided in the application. The multi-phase clock generator includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit includes a plurality of first delay circuits. The first oscillator circuit receives the first number of multi-phase input clock signals and outputs the second number of first output clock signals, wherein the second number is larger than the first number. The second oscillator circuit is coupled to the first oscillator circuit. The second oscillator circuit includes a plurality of second delay circuits. The second oscillator circuit receives the second number of first output clock signals and outputs the second number of second output clock signals. The number of second delay circuits is less than the number of first delay circuits.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.