Sample-and-hold-based retimer supporting link training
US11743080B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2020 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Oct 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/0349
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A linear retimer includes an equalizer, a clock recovery circuit, a sample and hold (S/H) circuit, and a linear driver. The equalizer receives an input signal and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal. The S/H circuit receives the equalized signal and the clock signal and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal. The S/H circuit is configured to preserve a voltage of the equalized signal in the retimed signal. In some examples, the S/H circuit is part of a linear three-tap feedforward equalizer, and the linear driver receives an output of the feedforward equalizer. The linear retimer can be placed between a transmitter and a channel or after the channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.