Vertical memory devices and methods of manufacturing the same
US11744077B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Feb 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mold including insulation layers and sacrificial layers is formed on a substrate. A channel hole is formed through the mold. A first deposition process is performed using a first precursor including silane and a second precursor including silane and a halogen element to form a first preliminary blocking layer on a sidewall of the channel hole. A second deposition process is performed using the first precursor to form a second preliminary blocking layer on the sidewall of the channel hole. The first and second preliminary blocking layers form a third preliminary blocking layer. An oxidation process is performed on the third preliminary blocking layer to transform the third preliminary blocking into a first blocking layer. A charge storage layer, a tunnel insulation layer, and a channel layer are formed on the first blocking layer. The sacrificial layer is replaced with a gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.