Data processing method for improving access performance of memory device and data storage device utilizing the same
US11748032B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 4, 2021 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | Jan 27, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device includes a memory device including multiple memory blocks corresponding to multiple logical units and a memory controller. The memory controller accesses the memory device and updates content of an activated count table in response to a command issued by a host device. One or more sub-regions to be activated are identified in the command. The activated count table includes a plurality of fields each recording an activated count associated with one sub-region. The memory controller updates content of the activated count table by increasing one or more activated counts associated with the one or more sub-regions identified in the command. The memory controller further selects at least one sub-region according to the content of the activated count table and performs a data rearrangement procedure to move data of the selected at least one sub-region to a first memory space having continuous physical addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.