Fine grain level memory power consumption control mechanism
US11748249B2 · kind B2 · utility
0Cited by
11References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 13, 2022 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | May 13, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one general aspect, an apparatus may include a memory module. The memory module may include a plurality of memory banks configured to store data. The memory module may include a plurality of memory bank power down controllers, each configured to place one or more respective memory bank(s) in a power down mode. The memory module may include a memory module command interface configured to receive a handshake command from a memory controller, wherein the handshake command comprises a command to remove an indicated memory bank from power down mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.