Automated analog layout
US11748538B1 · kind B1 · utility
0Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2022 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | Mar 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.