Method of manufacturing a power semiconductor component arrangement or a power semiconductor component housing

US11749533B2 · kind B2 · utility

Assignee

• Fraunhofer-Gesellschaft zur förderung der angewandten Forschung e.V. · DE

Inventors

• Steffen Ziesche · Erlangen, DE
• Christian Lenz · Hamburg, DE
• Uwe Waltrich · Forchheim, DE
• Christoph Bayer · Erlangen, DE
• Hoang Linh Bach · Erlangen, DE
• Andreas Schletz · Etzenricht, DE

Key dates

• Filing date: Apr 19, 2021
• Grant date: Sep 5, 2023
• Expiry date: Jun 3, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2224/18
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed is a method of manufacturing a power semiconductor component arrangement or a power semiconductor component housing. The method involves a sintering process in which the plurality of layer-shaped unsintered ceramic substrates are converted into a sintered ceramic single layer or multilayer substrate or into a sintered ceramic single layer or multilayer interconnect device. Also disclosed is a power semiconductor component arrangement or a power semiconductor component housing that can be manufactured using the above method. Further disclosed are the uses of the power semiconductor component arrangement or the power semiconductor component housing.