Integrated circuit structure
US11749679B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2021 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | Jul 9, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0128
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An IC fabrication method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.