Array substrate, method for fabricating same, and display panel
US11749687B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2020 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | Apr 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/451
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate, a method for fabricating the same, and a display panel are provided. The array substrate includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer. The first metal layer includes a first data line and a first vertical scan line. The second metal layer includes a horizontal scan line. The third metal layer includes a second data line and a second vertical scan line. The second data line is connected to the first data line through a first via hole. The second vertical scan line is connected to the first vertical scan line through a second via hole. The second vertical scan line is connected to the horizontal scan line through a third via hole. The first via hole, the second via hole, and the third via hole are formed by a same manufacturing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.