Flip-flop with input and output select and output masking that enables low power scan for retention
US11750178B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 2021 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | Nov 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop including a scan enable input for receiving a scan enable signal, a clock input for receiving a clock signal, input select circuitry that is configured to select between a data input and a scan input based on a state of the scan enable signal for providing a selected input, latching circuitry that is configured to latch the selected input to a preliminary output node in response to transitions of the clock signal, and output select circuitry that is configured to provide a state of the preliminary output node to a selected one of a scan output and a data output based on a state of the scan enable signal. The flip-flop may be implemented using fast yet leaky transistors. The data output may be disabled to prevent toggling other circuitry when scanning into or out of a memory for data retention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.