Receiver synchronization for higher speed passive optical networks
US11750290B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2020 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | May 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0047
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An optical network receiver (ONU) circuit associated with a passive optical network (PON) is disclosed. The ONU circuit comprises one or more processors is configured to operate in a hunt state, wherein the one or more processors is configured to detect frame boundaries associated with an incoming data signal based on a detecting a predefined synchronization (psync) pattern associated with the incoming data signal and transition to a pre-sync state, when the predefined psync pattern is detected correctly. The one or more processors is further configured to operate in the pre-sync state, wherein the one or more processors is configured to perform forward error correction (FEC) decoding for the incoming data signal, in order to determine signal statistics associated with the incoming data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.