Electromagnetic interference suppression circuit and related sensing circuit
US11754611B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2020 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Mar 18, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/001
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electromagnetic interference suppression circuit and a related sensing circuit. The sensing circuit includes an input and an output operatively coupled with the input. The input is adapted to be connected on a power line and in series between a load and a shunt circuit connected across power lines between a power source and the load. The output is adapted to provide a signal (Vs) associated with an electromagnetic interference signal (Vn) generated by or at the load and arranged to be experienced by the shunt circuit. The signal (Vs) can be used for determining a suppression signal (Vn′) for reducing, or substantially eliminating, the electromagnetic interference signal (Vn). The electromagnetic interference suppression circuit includes the sensing circuit, a regulator circuit, and a controlled signal source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.