Monitoring transitions of a circuit
US11755342B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2020 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Nov 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a guard trigger circuit that includes a first input node adapted to be coupled to a first state signal, a second input node adapted to be coupled to a second state signal and an output node. The circuit also includes a reset synchronizer circuit that includes an input node coupled to the output node of the guard trigger circuit, a clock node adapted to be coupled to a clock signal and an output node. The circuit further includes a timeout circuit including an input node coupled to the output node of the reset synchronizer circuit, a clock node adapted to be coupled to the clock signal and an output node. The circuit still further includes a reset requestor circuit that includes a first input node coupled to the output node of the guard trigger circuit, a second node coupled to the output node of the timeout circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.