Techniques for handling escalation of interrupts in a data processing system
US11755362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2021 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Jun 7, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4818
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques of handling interrupt escalation are implemented in hardware. In at least one embodiment, an interrupt presentation controller (IPC) receives an event notification message requesting an interrupt, specifying an interrupt priority, and referencing a virtual processor (VP) thread. The IPC determines whether the VP thread matches any interruptible VP thread. If not, the IPC conditionally escalates the interrupt requested by the event notification message. Conditionally escalating the interrupt includes determining whether or not the interrupt priority is greater than the operating priority of any interruptible VP thread. If so, the IPC initiates escalation of the interrupt requested by the event notification message to a next higher software stack level by issuing an escalate message. If not, the IPC refrains from escalating the interrupt requested by the event notification message.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.