Method for predicting delay at multiple corners for digital integrated circuit
US11755807B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2022 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Mar 9, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S10/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed in the present invention is a method for predicting a delay at multiple corners for a digital integrated circuit, which is applicable to the problem of timing signoff at multiple corners. In the aspect of feature engineering, a path delay relationship at adjacent corners is extracted by using a dilated convolutional neural network (Dilated CNN), and learning is performed by using a bi-directional long short-term memory model (Bi-directional Long Short-Term Memory, BLSTM) to obtain topology information of a path. Finally, prediction results of a path delay at a plurality of corners are obtained by using an output of a multi-gate mixture-of-experts network model (Multi-gate Mixture-of-Experts, MMoE). Compared with a conventional machine learning method, the present invention can achieve prediction with higher precision through more effective feature engineering processing in a case of low simulation overheads, and is of great significance for timing signoff at multiple corners of a digital integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.