Block erase type detection using bit count check
US11756637B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2021 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | May 5, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a power loss event has occurred, determine that one or more blocks are in an erased state, examine a block of the one or more blocks to determine whether the block is a SLC erased block or a TLC erased block, and place the block in a SLC pre-erase heap if the block is the SLC erased block or in a TLC pre-erase heap if the block is the TLC erased block. The controller is further configured to determine a first bit count of page0 for a SLC voltage for the block, determine a second bit count of page1 for a TLC voltage for the block, and classify the block as either a SLC erased block or a TLC erased block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.