Semiconductor memory device
US11756898B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2020 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Nov 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes: two memory blocks; a first structure disposed between the two memory blocks; and a second structure separated from the two memory blocks, or a plurality of second structures. The two memory blocks include a plurality of first conductive layers and a plurality of first insulating layers alternately arranged. The first structure has one end, and the one end is closer to the substrate than the plurality of first conductive layers are. The second structure has one end, and the one end is closer to the substrate than at least apart of the first conductive layers among the plurality of first conductive layers is. Another end of the first structure and another end of the second structure are farther from the substrate than the plurality of first conductive layers are. The second structure is separated from the first structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.