Method for processing a semiconductor wafer, semiconductor wafer, clip and semiconductor device

US11756917B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Carsten von Koblinski · Velden am Wörther See, AT
• Daniel Pedone · Munich, DE
• Matteo Piccin · Villach, AT
• Roland Rupp · Achern, DE
• Chiew Li Tai · Melaka City, MY
• Jia Yi Wong · Melaka City, MY

Key dates

• Filing date: Mar 16, 2021
• Grant date: Sep 12, 2023
• Expiry date: May 26, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2224/84345
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components.