Integrated circuit including asymmetric decoupling cell and method of designing the same
US11756949B2 · kind B2 · utility
0Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2021 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Nov 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes at least one decoupling cell, wherein the at least one decoupling cell includes at least one P-type decoupling MOSFET and at least one N-type decoupling MOSFET, and a number of the at least one P-type decoupling MOSFET is different from a number of the at least one N-type decoupling MOSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.