Method for dynamically adjusting adjustable gain value to equalize input signal to generate equalizer output signal and associated leveling equalizer
US11757420B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 19, 2021 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Aug 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G2201/106
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A leveling equalizer includes a graphic equalizer circuit, a first multiplication circuit, a second multiplication circuit, an addition circuit, and a gain control circuit. The graphic equalizer circuit processes a first input signal and output a first output signal and a second output signal. The first multiplication circuit multiplies the first output signal and one of an adjustable gain value and a fixed gain value to generate a first adjusted output signal. The second multiplication circuit multiplies the second output signal and another of the adjustable gain value and the fixed gain value to generate a second adjusted output signal. The addition circuit combines the first adjusted output signal and the second adjusted output signal to generate an equalizer output signal. The gain control circuit dynamically adjusts the adjustable gain value according to the equalizer output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.