Patent · US Active

Continuous-time input-stage successive approximation register analog-to-digital converter

US11757461B2 · kind B2 · utility

0Cited by

4References

25Claims

0Family size

Assignee

The Board of Regents of the University of Texas System · US

Inventors

Linxiao Shen · Austin, US
Nan Sun · Beijing, CN

Key dates

Filing date	Feb 12, 2020
Grant date	Sep 12, 2023
Priority date	—
Expiry date	Feb 12, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH03M1/468
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The exemplified disclosure presents a successive approximation register analog-to-digital converter circuit that comprises a two-step (e.g., two-stage) analog-to-digital converter (ADC) that operates a 1st-stage successive approximation register (SAR) in the continuous time (CT) domain (also referred to as a “1-st stage CTSAR”) that then feeds a sampling operation location in the second stage. Without a front-end sampling circuit in the 1st-stage, the exemplary successive approximation analog-to-digital converter circuit can avoid high sampling noise associated with such sampling operation and thus can be configured with a substantially smaller input capacitor size (e.g., at least 20 times smaller) as compared to conventional Nyquist ADC with a front-end sample-and-hold circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.