PAM-4 receiver with jitter compensation clock and data recovery

US11757613B2 · kind B2 · utility

Assignee

• The Hong Kong University of Science and Technology

Inventors

• Chik Patrick Yue · Milpitas, US
• Li Wang · Ji'an, CN

Key dates

• Filing date: May 16, 2022
• Grant date: Sep 12, 2023
• Expiry date: May 16, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L7/0008
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A PAM-4 receiver with jitter compensation clock and data recovery is provided. The receiver includes a first-order delay-locked loop (DLL) which employs a bang-bang phase detector (BBPD) and a voltage-controlled delay line (VCDL) circuit supporting 40 MHz jitter tracking bandwidth and static phase skew elimination. A second-order wideband phase-locked loop (WBPLL) using the ¼-rate reference clock provides multi-phase clock generation with low input-to-output latency. To suppress the consequent jitter transfer, a jitter compensation circuit (JCC) acquires the jitter transfer amplitude and frequency information by detecting the DLL loop filter voltage (VLF(s)) signal, and generates an inverted loop filter voltage signal, denoted as VLFINV(s). The VLFINV(s) modulates a group of complementary VCDLs (C-VCDLs) to attenuate the jitter transfer on both recovered clock and data. With the provided receiver, a jitter compensation ratio up to 60% can be supported from DC to 4 MHz, with a −3-dB corner frequency of 40 MHz.