Data processing apparatus and data accessing circuit
US11762772B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2021 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Nov 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus including a memory circuit and a data accessing circuit is provided, in which the memory circuit includes multiple cache ways configured to store data. In response to a first logic state of an enabling signal, if a tag of an address of an access requirement is the same as a corresponding tag of the multiple cache ways, the data accessing circuit determines that a cache hit occurs. In response to a second logic state of the enabling signal, if the address is within one or more predetermined address intervals specified by the data accessing circuit, the data accessing circuit determines that the cache hit occurs, and if the address is outside the one or more predetermined address intervals, the data accessing circuit determines that a cache miss occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.