Arithmetic processor and method for operating arithmetic processor
US11762774B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2022 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Apr 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arithmetic processor including a plurality of core groups each including a plurality of cores and a cache unit, a plurality of home agents each including a tag directory and a store command queue and a store command queue. The store command queue enters the received store request to the entry queue in order of reception, the cache unit stores the data of the store request in a data RAM. The store command queue sets a data ownership acquisition flag of the store request to valid when obtaining a data ownership of the store request and issues a top-of-queue notification to the cache control unit when the flag of the top-of-queue entry is valid. In response to the top-of-queue notification, the cache unit update a cache tag to modified state and issue a store request completion notification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.