Patent · US Active

Compression for deep learning in case of sparse values mapped to non-zero value

US11763183B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Ajit Singh · Plainsboro, US
Bharat Daga · Fremont, US
Michael Behar · Jerusalem, IL

Key dates

Filing date	Jul 30, 2021
Grant date	Sep 19, 2023
Priority date	—
Expiry date	Nov 23, 2041

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the encode circuit, writes encoded neural network data to a memory device coupled with the processing apparatus, writes metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decodes encoded neural network data via the decode circuit in response to a request from the compute circuitry.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.