Computational architecture for active noise reduction device
US11763794B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2022 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Jun 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04R1/1016
- WIPO fieldOther consumer goods
- WIPO sectorOther fields
Abstract
Various implementations include a method for implementing a computational architecture for a personal active noise reduction (ANR) device. A method includes receiving a source audio stream with a first DSP and performing ANR on the source audio stream utilizing operational parameters stored in the first DSP; outputting a processed audio stream from the first DSP; generating state data with a second DSP in response to an analysis of at least one of the source audio stream, microphone inputs and the processed audio stream, and communicating signals to the first DSP over a common bus coupled to the first and second DSPs to alter the operational parameters in the first DSP; and utilizing a general purpose processor coupled to both the first DSP and the second DSP to communicate control signals with a communication interface, process state data from the second DSP, and alter the operational parameters in the first DSP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.