Semiconductor encapsulation structure and encapsulation method
US11764163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2021 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Dec 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01Q1/2208
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a semiconductor encapsulation structure and an encapsulation method. The structure includes a circuit board, which includes at least one electromagnetic shield area and a non-electromagnetic shield area located on one side of the electromagnetic shield area, where the circuit board internally includes a number N of metal line layers stacked in sequence and insulating layers located between adjacent metal line layers; a non-shield module and a shield module, where the non-shield module is located within the non-electromagnetic shield area, and the shield module is located within the electromagnetic shield area; a thin film encapsulation layer, located on a side of the circuit board adjacent to the first surface, where the thin film encapsulation layer covers the non-electromagnetic shield area and the electromagnetic shield area; an electromagnetic shield structure, which covers the electromagnetic shield area and forms the closed space with the circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.