Self-aligned vertical solid state devices fabrication and integration methods
US11764199B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2019 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Aug 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/825
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments include methods of fabricating an array of self-aligned vertical solid state devices and integrating the devices to a system substrate. The method of fabricating a self-aligned vertical solid state device comprising: providing a semiconductor substrate, depositing a plurality of device layers on the semiconductor substrate, depositing an ohmic contact layer on an upper surface of one of the plurality of device layers, wherein the device layers comprises an active layer and a doped conductive layer, forming a patterned thick conductive layer on the ohmic contact layer; and selectively etching down the doped conductive layer that does not substantially etch the active layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.