Processing system, related integrated circuit, device and method
US11764807B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 6, 2022 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Jul 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/611
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits. For example the safety monitor circuit comprises a test circuit configured to provide modified data bits and/or modified ECC bits to the error detection circuit as a function of connectivity test control signals, whereby the error detection circuit asserts the error signal as a function of the connectivity test control signals.…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.