Extendable parity code matrix construction and utilization in a data storage device
US11764813B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2022 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Jun 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6566
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Example channel circuits, data storage devices, and methods for using an extendable parity code matrix are described. A data unit may be read from a storage medium. Multiple sets of parity bits may be available for the data unit, each set of parity bits having a different number of parity bits corresponding to different parity matrices, including a primary parity matrix and at least one extended parity matrix. The extended parity matrix includes the primary parity matrix and additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data unit based on the data unit from the read signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.