Semiconductor devices including a buried gate electrode
US11765885B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2021 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Apr 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a substrate including a recess; a gate insulation layer on a surface of the recess; a first gate pattern on the gate insulation layer and filling a lower portion of the recess; a second gate pattern on the first gate pattern in the recess and including a material having a work function different from a work function of the first gate pattern; a capping insulation pattern on the second gate pattern and filling an upper portion of the recess; a leakage blocking oxide layer on the gate insulation layer at an upper sidewall of the recess above an upper surface of the first gate pattern and contacting a sidewall of the capping insulation pattern; and impurity regions in the substrate and adjacent to the upper sidewall of the recess, each impurity region having a lower surface higher than the upper surface of the first gate pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.